A microprocessor is a digital device that is utilized to execute instructions defined within a computer program. Such instructions include adding two data values together, comparing data values, moving data from one location to another, etc. In addition, a microprocessor is designed to communicate with other devices, such as network controllers, disk drives, keyboards, displays, etc., that are external to it. Typically, such external devices request the attention of the microprocessor by signaling one of several interrupt lines on the microprocessor. When this occurs, the microprocessor halts program execution, runs a special program called an “exception handler” to determine which device requested the interrupt, and what the nature of the interrupt is. Once the microprocessor has determined the nature of the interrupt, it executes an interrupt routine that is specific to the nature of the interrupt. Upon completion, the microprocessor typically returns to the program it was executing before the interrupt occurred.
One skilled in the art will appreciate that the above description of interrupt handling is very simplistic. That is, it has not considered the difference between hardware interrupts, software interrupts, internal exceptions, etc., nor has it considered what occurs when multiple interrupts occur simultaneously, or when a second interrupt occurs during processing of a first interrupt. However, the way a microprocessor handles an interrupt is, in many ways, dependent on the specific architecture of the microprocessor. For purposes of illustrating the present invention, an interrupt problem will be described with particular reference to the architecture of MIPS32™ and MIPS64™ microprocessors (hereinafter MIPS® microprocessors) designed by MIPS Technologies, Inc. of Mountain View, Calif.
More specifically, like many modern microprocessors, MIPS microprocessors contain privileged architecture registers that are updated during events such as interrupts and exceptions. These registers are not directly accessible by user programs that execute on the microprocessors. Rather, when an interrupt or exception occurs, program execution is halted, and a special program, called an exception handler, is run which accesses the privileged architecture registers, both to determine the nature of the interrupt, and to set or clear bits within one or more of the registers, which control how the interrupt will be handled. (Note: The exception handler typically resides within an area of memory that can only be accessed by the microprocessor if it is in “kernel” mode. That is, to prevent user programs from accessing or changing the contents of the privileged architecture registers, a task switch must first occur which authorizes the execution of the exception handler, and thus access to the registers.) Once the exception handler has read the appropriate privileged registers, and established how the interrupt will be handled, an interrupt service routine is used to service the interrupt. Upon completion of servicing the interrupt, the exception handler returns execution to the user program.
A particular privileged architecture register within a MIPS microprocessor is called the status register (SR). The SR contains a number of bit fields that may be examined, and set or cleared, during handling of an interrupt. Like most privileged architecture registers, the SR register cannot be modified directly. Rather, the process for examining and modifying the contents of the SR register involves the steps of: 1) Reading the contents of the SR register into one of the general purpose registers within the microprocessor; 2) Modifying, or setting/clearing particular bits within the general purpose register that contains the contents of the SR register; and 3) Writing the modified contents of the general purpose register back into the SR register. This three-step process is referred to as a R-M-W sequence, and is often required during interrupt processing.
Sample program code that performs this R-M-W sequence is shown below:
LabelInstructionOperandsmfc0t0, SR1:ort0, things_to_setandt0, things_to_preserve2:mtc0t0, SR
The first instruction “mfc0” causes the microprocessor to move the contents of the SR register into a general purpose register designated t0. This is the read cycle. The next two instructions “or” and “and” set or preserve particular bits within the t0 register, corresponding to the “things_to_set” mask, or the “things_to_preserve” mask. This is the modify cycle. The fourth instruction “mtc0” causes the microprocessor to move the contents of the t0 register back into the SR register. This is the write cycle. Specifics relating to which of the SR bits are modified during an interrupt, how the above instructions operate and other information related to the MIPS32 and MIPS64 architectures can be found in the following references, each of which is available from MIPS Technologies, Inc. and incorporated herein by reference in its entirety for all purposes:    1. MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32 Architecture, MIPS Technologies, Inc. (2002);    2. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set, MIPS Technologies, Inc. (2002);    3. MIPS32 Architecture For Programmers Volume III: The MIPS32 Privileged Resource Architecture, MIPS Technologies, Inc. (2002);    4. MIPS64 Architecture For Programmers Volume I: Introduction to the MIPS64 Architecture, MIPS Technologies, Inc. (2002);    5. MIPS64 Architecture For Programmers Volume II: The MIPS64 Instruction Set, MIPS Technologies, Inc. (2002);    6. MIPS64 Architecture For Programmers Volume III: The MIPS64 Privileged Resource Architecture, MIPS Technologies, Inc. (2002);
During execution of an interrupt service routine, it may be desirable to perform the above described R-M-W sequence. One problem that exists is that the R-M-W sequence may itself be interrupted. For example, suppose that the R-M-W sequence described above is executing in response to a first interrupt. Further, suppose a second interrupt occurs between label 1 and label 2 above. The processor might halt execution of this R-M-W sequence and begin servicing the second interrupt. Now, suppose that while servicing the second interrupt, the contents of the SR register are changed. Upon return from servicing the second interrupt, the code at label 2 will write its altered value into SR, but will lose any changes made to the SR register by the second interrupt routine. Such a situation is unacceptable since changes to the SR register cannot be ignored.
In response to the above problem, several solutions have been developed to prevent changes in the SR register from being lost or ignored. A first solution is to simply disable all interrupts prior to performing the R-M-W sequence above. However, this situation is a catch-22, because in order to disable interrupts, interrupt mask bits in the SR register must be cleared, the clearing of which requires the same R-M-W sequence! What happens if an interrupt occurs while executing the R-M-W sequence that disables interrupts? One method of solving this problem is to insist that no interrupt change the value of SR during execution of any interrupt code. That is, by requiring that all interrupt code begin by saving off the value of SR, and end by restoring the saved value of SR back into SR, it can be assured that the SR value doesn't change. In many environments, however, this is considered too restrictive, as well as too time consuming. Moreover, in operating environments where interrupt routines are not strictly nested, you can never be sure you return to the spot where the proper SR value can be restored.
A second solution is to use a system call to disable interrupts. A system call works by causing an exception that disables interrupts in a single cycle. Then, the R-M-W sequence can proceed without risk of interruption. Many programmers consider use of a system call, to simply overcome the inherent problems of updating the SR register, overly dramatic, and again, too time consuming.
Therefore, what is needed is a mechanism that allows a programmer to set or clear bits within a privileged architecture register of a processor, while guaranteeing that the modification process is not interrupted.
Furthermore, what is needed is a method and apparatus that sets or clears selected portions of a privileged architecture register atomically (i.e., within a single non-interruptible instruction). By modifying privileged bits atomically, the above presented problems associated with the R-M-W sequence are solved without imposing any additional processing delays, and without insisting that interrupt routines be strictly nested.
Furthermore, what is needed is a method and apparatus for encoding within an instruction, what privileged architecture register is to be affected by the instruction, what bits are to be set or cleared within the control register, and where the previous contents of the control register are to be saved (if requested).